1. Field of the Invention
This invention relates to computing systems, and more particularly, to efficiently powering down banks in a cache memory for reducing power consumption.
2. Background
A microprocessor may be coupled to one or more levels of a cache hierarchy in order to reduce the latency of the microprocessor's request of data in memory for a read or a write operation. Generally, a cache may store one or more blocks, each of which is a copy of data stored at a corresponding address in the system memory. Since caches have finite sizes, the total number of cache blocks is inherently bounded. Additionally, there may be a limit on the number of blocks that map to a given set in a set-associative cache. However, there may be conditions that benefit from a finer limit on a number of cache blocks associated with a given cache property than a limit offered by the cache capacity or the cache associativity. Examples of the cache property may include one or more of a coherence state, a dirty state, a source ownership state, a remote state that may be used in a non-uniform memory access (NUMA) computing system, and so forth.
Providing the finer limit on the number of cache blocks associated with the given cache property may reduce latencies for searching for the number of cache blocks and moving the number of cache blocks prior to setting the cache in a different state. The different state may be a low-power mode. Alternatively, the different state may be a power-up mode for a given portion in the cache memory. Additionally, the finer limit may reduce a number of conflict misses for a set-associative or a direct-mapped cache for both cache blocks with and without the cache property.
Further, the latency for the cache to transition to a given state, such as a low-power mode, may be reduced with the finer limit. For example, to manage power consumption, chip-level and system-level power management systems typically disable portions of the chip or system when experiencing no utilization for a given time period. However, transitioning portions of the cache to a low-power mode and later returning to an active mode may be delayed until the number of cache blocks associated with the cache property are each migrated to another portion or evicted and written back to lower-level memory. Without the finer limit, the transition latency may be too large. The large latency may reduce both the benefits of the power management system and the number of times the transition actually occurs despite the power management system notifications.
In view of the above, efficient methods and systems for efficiently powering down banks in a cache memory for reducing power consumption are desired.